CREDITS: Steve VanDevender is primarily responsible for the design, organization, and content of this document. Information was obtained from the "HP 48 System RPL Tools" documentation, and "The Rosetta Stone: HP <-> AG Mnemonics", originally compiled by Joseph K. Horn, updated by Jan Brittenson. Joseph K. Horn also provided additional information not available in the other two documents. Alonzo Gariepy is the designer of the assembly language mnemonics and syntax primarily used in this document. The particular assembler syntax used is that of Jan Brittenson's STAR assembler. While some information on the original HP mnemonics is provided, I chose AG mnemonics for several reasons: The widely available STAR assembler and MLDL debugger packages written by Jan Brittenson use them exclusively, and I personally find them easier to understand and am guessing that other experienced assembly language programmers will find them more in the style of those used by other microprocessor assembly languages. SYMBOL KEY In tables, the left column shows what the symbol represents in instruction mnemonics or operands, and the right column shows what the symbol represents in opcodes or other instruction data. b: branch displacement. May be 2, 3, or 4 nibs sign-extended to 5 nibs for a relative branch displacement, or a 5-nib absolute address, specifying the branch target. The displacement is stored with the least-significant nibble in the lowest address. d: data pointer register. D0 0 D1 1 f, g: register field specifiers. .f/.g f g .P 000 0000 .WP 001 0001 .XS 010 0010 .X 011 0011 .S 100 0100 .M 101 0101 .B 110 0110 .W 111 0111 .A 1111 h: hexadecimal immediate data. L: length of data operated on by instruction (in nibs). (This appears capitalized in the instruction summary to avoid confusing 'l' with '1'.) .Pn n n nibs in register starting at P. .n n n nibs in register starting at 0. .P 1 1 nib in register at P. .WP P+1 Word to P, nibs 0 to P. .XS 1 eXponent Sign, nib 2. .X 3 eXponent, nibs 0-2. .S 1 mantissa Sign, nib 15. .M 12 Mantissa, nibs 3-14. .B 2 Byte, nibs 0-1. .W 16 Word, nibs 0-15. .A 5 Address, nibs 0-4. m: specifies a register that can interact with memory (an m-register). A 0 C 1 n: numeric specifer (mnemonic/operand form) in the range 1-16. Opcode contains xxxx = n - 1. r, s: general register. A single-operand instruction codes only r in rr. Two-operand instructions code both r and s in rr. r s rr - - -- A B 00 B C 01 C A 10 D C 11 t: temporary register (or t-register). R0 000 R1 001 R2 010 R3 011 R4 100 x: numeric specifier (opcode form). Mnemonic followed by .n where n = x + 1. REGISTER MODEL Field specifiers: These examples use P = 8, n = 6. .Pn is equivalent to .n if P = 0. | .n | | .Pn | |.P| | .WP | ------------------------------------------------- |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| ------------------------------------------------- |.S| .M |XS| .B | | .X | | .A | | .W | <- left right -> <- most significant least significant -> read from/written to <- higher addresses lower addresses -> Main registers: A and C are referred to as "m-registers" because they interact with memory. ------------------------------------------------- |15 0| A <--> | ------------------------------------------------- | |15 0| B | memory ------------------------------------------------- | |15 0| C <--> | ------------------------------------------------- |15 0| D ------------------------------------------------- ---- | 0| P ---- Address registers: ------------------- |4 0| D0 ------------------- |4 0| D1 ------------------- ------------------- |4 0| PC ------------------- Return stack registers: RST0 is top of stack. An item is pushed on the stack by copying RST6 to RST7, RST5 to RST6, . . . RST0 to RST1, then placing the item in RST0. The stack is popped by copying RST0 to a destination, then copying RST1 to RST0, RST2 to RST1, . . . RST7 to RST6, then placing 0 in RST7. ------------------- |4 0| RST0 ------------------- . | . . . | . ------------------- . |4 0| RST7 ------------------- Status register: bit 15 bit 0 ---------------- |3 | 0| ST ---------------- HST ST bit 15 12 ------------- |MP|SR|SB|XM| HST bits ------------- MP = Module Pulled (set when an expansion moduled is removed) SR = System Request (set when an I/O request is pending) SB = Sticky Bit (set when certain shift operations shift out a 1 bit or 1 nibble) XM = eXternal Module Missing bit (set by RETSETXM). Temporary registers: These are referred to as "t-registers". ------------------------------------------------- |15 0| R0 ------------------------------------------------- |15 0| R1 ------------------------------------------------- |15 0| R2 ------------------------------------------------- |15 0| R3 ------------------------------------------------- |15 0| R4 ------------------------------------------------- INSTRUCTION SUMMARY Format: OPCODE operands Description of instruction operation. OPCODE.f operands [opcode in binary, grouped into nibbles] cycles: n (r/w) note: (if any) Flags affected: Description of effect on CPU flags (Carry flag or HST flags). operands: "src" refers to a source operand. "dst" refers to a destination operand, or to the operand of a single-operand instruction. "target" refers to a branch target. "n" refers to an immediate or numeric operand. n: number of clock cycles used by instruction. May depend on length of operand fields. r: number of memory reads done by instruction w: number of memory writes done by instruction Memory cycle information is provided for Saturn processors (like the HP 48 Clarke) that have different cycle times for internal operations and memory references. The HP 48 Clarke CPU has a 500 ns cycle time for internal operations but a 1000 ns time for memory references. Adding together the n, r, and w fields of a timing description, then dividing by 2, should give the Clarke instruction timing in microseconds. ADD src, dst Add src to dst. register to register: ADD.f s, r 1010 0fff 00rr ADD.f r, r 1010 0fff 01rr ADD.f r, s 1010 0fff 10rr cycles: 3+L (3/0) ADD.A s, r 1100 00rr ADD.A r, r 1100 01rr ADD.A r, s 1100 10rr cycles: 7 (2/0) ADD.A P+1, C 1000 0000 1001 cycles: 8 (3/0) note: always performed in HEX mode immediate to register: ADD.g n, r 1000 0001 1000 gggg 00rr xxxx cycles: 5+L (6/0) note: always performed in HEX mode ADD.A n, d 0001 011d xxxx cycles: 7 (3/0) note: always performed in HEX mode Flags affected: Carry is set if overflow from most significant nib, cleared otherwise. AND src, dst Compute logical AND of src and dst. AND.g s, r 0000 1110 gggg 00rr AND.g r, s 0000 1110 gggg 01rr cycles: 4+L (4/0) Flags affected: None. BRBC n, reg, target Add displacement to PC if bit n of reg is clear (0). Displacement is relative to nib following '.'. BRBC h, A, PC+5+b 1000 0000 1000 0110 hhhh.bbbb bbbb BRBC h, C, PC+5+b 1000 0000 1000 1010 hhhh.bbbb bbbb cycles: 16 (branch taken) (7/0) 9 (not taken) BRBC h, ST, PC+3+b 1000 0110 hhhh.bbbb bbbb cycles: 14 (branch taken) (5/0) 7 (not taken) Add displacement to PC if HST AND h is 0. BRBC h, HST, PC+3+b 1000 0011 hhhh.bbbb bbbb cycles: 13 (branch taken) (5/0) 6 (not taken) Flags affected: Carry is set if branch is taken, cleared if branch is not taken. BRBS n, reg, target Add displacement to PC if bit n of reg is set (1). Displacement is relative to nib following '.'. BRBS h, A, PC+5+b 1000 0000 1000 0111 hhhh.bbbb bbbb BRBS h, C, PC+5+b 1000 0000 1000 1011 hhhh.bbbb bbbb cycles: 16 (branch taken) (7/0) 9 (not taken) BRBS h, ST, PC+3+b 1000 0111 hhhh.bbbb bbbb cycles: 14 (branch taken) (5/0) 7 (not taken) Flags affected: Carry is set if branch is taken, cleared if branch is not taken. BRCC target Add displacement to PC if carry flag is clear. Displacement is relative to nib following '.'. BRCC PC+b+1 0101.bbbb bbbb cycles: 10 (branch taken) (3/0) 3 (not taken) Flags affected: None. BRCS target Add displacement to PC if carry flag is set. Displacement is relative to nib following '.'. BRCS PC+b+1 0100.bbbb bbbb cycles: 10 (branch taken) (3/0) 3 (not taken) Flags affected: None. BREQ src1, src2, target Add displacement to PC if register fields are EQual. Displacement is relative to nib following '.'. BREQ.A r, s, PC+b+3 1000 1010 00rr.bbbb bbbb BREQ.f r, s, PC+b+3 1001 0fff 00rr.bbbb bbbb cycles: 13+L (branch taken) (5/0) 6+L (not taken) Add displacement to PC if P is EQual to h. BREQ.1 P, h, PC+b+3 1000 1001 hhhh.bbbb bbbb cycles: 13 (branch taken) (5/0) 6 (not taken) Flags affected: Carry is set if branch is taken, cleared if not taken. BRGE src1, src2, target Add displacement to PC if src1 is Greater than or Equal to src2. Displacement is relative to nib following '.'. BRGE.f r, s, PC+b+3 1001 1fff 10rr.bbbb bbbb BRGE.A r, s, PC+b+3 1000 1011 10rr.bbbb bbbb cycles: 13+L (branch taken) (5/0) 6+L (not taken) Flags affected: Carry is set if branch is taken, cleared if not taken. BRGT src1, src2, target Add displacement to PC if src1 is Greater Than src2. Displacement is relative to nib following '.'. BRGT.f r, s, PC+b+3 1001 1fff 00rr.bbbb bbbb BRGT.A r, s, PC+b+3 1000 1011 00rr.bbbb bbbb cycles: 13+L (branch taken) (5/0) 6+L (not taken) Flags affected: Carry is set if branch is taken, cleared if not taken. BRLE src1, src2, target Add displacement to PC if src1 is Less than or Equal to src2. Displacement is relative to nib following '.'. BRLE.f r, s, PC+b+3 1001 1fff 11rr.bbbb bbbb BRLE.A r, s, PC+b+3 1000 1011 11rr.bbbb bbbb cycles: 13+L (branch taken) (5/0) 6+L (not taken) Flags affected: Carry is set if branch is taken, cleared if not taken. BRLT src1, src2, target Add displacement to PC if src1 is Less Than src2. Displacement is relative to nib following '.'. BRLT.f r, s, PC+b+3 1001 1fff 01rr.bbbb bbbb BRLT.A r, s, PC+b+3 1000 1011 01rr.bbbb bbbb cycles: 13+L (branch taken) (5/0) 6+L (not taken) Flags affected: Carry is set if branch is taken, cleared if not taken. BRNE src1, src2, target Add displacement to PC if src1 is Not Equal to src2. Displacement is relative to nib following '.'. BRNE.f r, s, PC+b+3 1001 0fff 01rr.bbbb bbbb BRNE.A r, s, PC+b+3 1000 1010 01rr.bbbb bbbb cycles: 13+L (branch taken) (5/0) 6+L (not taken) Add displacement to PC if P is Not Equal to h. BRNE.1 P, h, PC+b+3 1000 1000 hhhh.bbbb bbbb cycles: 13 (branch taken) (5/0) 6 (not taken) Flags affected: Carry is set if branch is taken, cleared if not taken. BRNZ reg, target Add displacement to PC if field in reg is Not Zero. Displacement is relative to nib following '.'. BRNZ.f r, PC+b+3 1001 0fff 11rr.bbbb bbbb BRNZ.A r, PC+b+3 1000 1010 11rr.bbbb bbbb cycles: 13+L (branch taken) (5/0) 6+L (not taken) Flags affected: Carry is set if branch is taken, cleared if not taken. BRZ reg, target Add displacement to PC if field in reg is Zero. Displacement is relative to nib following '.'. BRZ.f r, PC+b+3 1001 0fff 10rr.bbbb bbbb BRZ.A r, PC+b+3 1000 1010 10rr.bbbb bbbb cycles: 13+L (branch taken) (5/0) 6+L (not taken) Flags affected: Carry is set if branch is taken, cleared if not taken. BUSCB Reserved. Same as NOP (all devices ignore NSTR {Not STRobe line: system clock, active low} until a new command is loaded) for the internal peripherals. Not issued by the CPU. BUSCB 1000 0000 1000 0011 cycles: 7 (4/0) Flags affected: None. BUSCC The device currently addressed by its local data pointer performs a specific operation as defined by the individual device. This command is not issued by the CPU. BUSCC 1000 0000 1011 cycles: 6 (4/0) Flags affected: None. BUSCD Reserved. Same as NOP (all devices ignore NSTR {Not STRobe line: system clock, active low} until a new command is loaded) for the internal peripherals. Not issued by the CPU. BUSCD 1000 0000 1000 1101 cycles: 7 (4/0) Flags affected: None. CALL target Add displacement to PC after saving address of next instruction on return stack. Displacement is relative to beginning of next instruction. CALL.3 PC+b+4 0111 bbbb bbbb bbbb cycles: 12 (4/0) CALL.4 PC+b+6 1000 1110 bbbb bbbb bbbb bbbb cycles: 14 (6/0) Set PC to displacement after saving address of next instruction on return stack. CALL.A b 1000 1111 bbbb bbbb bbbb bbbb bbbb cycles: 15 (7/0) Flags affected: None. CLR dst Fill a register field with zeros. CLR.f r 1010 1fff 00rr cycles: 3+L (3/0) CLR.A r 1101 00rr cycles: 7 (2/0) CLR.X ST 0000 1000 cycles: 5 (2/0) Flags affected: None. CLRB n, dst Clear bit n of dst (make it 0). CLRB h, A 1000 0000 1000 0100 hhhh CLRB h, C 1000 0000 1000 1000 hhhh cycles: 6 (5/0) CLRB h, ST 1000 0100 hhhh cycles: 4 (3/0) Flags affected: None. Clear bits in HST corresponding to 1 bits in h. CLRB h, HST 1000 0010 hhhh cycles: 3 (3/0) Flags affected: Corresponding flags in HST. CONFIG Configures an unconfigured device that has DAISYIN=1 @C.A; it then will no longer respond to either the CONFIGURE or ID bus commands. CONFIG 1000 0000 0101 cycles: 11 (3/0) Flags affected: None. DEC dst Subtract one from a register field. DEC.f r 1010 0fff 11rr cycles: 3+L (3/0) DEC.A r 1100 11rr cycles: 7 (2/0) DEC.1 P 0000 1101 cycles: 3 (2/0) note: always performed in HEX mode Flags affected: Carry is set if dst is 0 before decrement, cleared otherwise. IN dst Move the input register to dst. IN.4 m 1000 0000 001m cycles: 7 (3/0) Flags affected: None. INC dst Add one to a register field. INC.f r 1011 0fff 01rr cycles: 3+L (3/0) INC.A r 1110 01rr cycles: 7 (2/0) INC.1 P 0000 1100 cycles: 3 (2/0) note: always performed in HEX mode Flags affected: Carry is set if dst is 0 after increment, cleared otherwise. INTOFF Masks maskable input register interrupts (ignore interrupts). Unmaskable interrupts (always available) are (1) NINTX line pulled low, which disables all interrupts and sets HS3 (aka MP, Module Pulled hardware status bit); (2) NINT2X, same as NINTX except no hardware status bits are set; and (3) IR15X line pulled high, readable via the input register commands A=IN (IN.4 A) and C=IN (IN.4 C). INTOFF 1000 0000 1000 1111 cycles: 5 (4/0) Flags affected: None. INTON Unmasks maskable input register interrupts (catch interrupts) on the KDN line. If KDN goes high while interrupts are off, it must remain high until INTON is executed to generate an interrupt. INTON 1000 0000 1000 0000 cycles: 5 (4/0) Flags affected: None. JUMP target Add displacement to PC. Displacement is relative to nib following '.'. JUMP.3 PC+b+1 0110.bbbb bbbb bbbb cycles: 11 (4/0) JUMP.4 PC+b+2 1000 1100.bbbb bbbb bbbb bbbb cycles: 14 (6/0) Set PC to displacement. JUMP.A b 1000 1101 bbbb bbbb bbbb bbbb bbbb cycles: 14 (7/0) Set PC to value in m-register's A-field. JUMP.A m 1000 0001 1011 001m cycles: 16 (5/0) Set PC to value in memory pointed to by m-register's A-field. JUMP.A @m 1000 0000 1000 11m0 cycles: 23 Flags affected: None. MOVE src, dst Move data between register fields or between a register field and memory. register to register: MOVE.f s, r 1010 1fff 01rr MOVE.f r, s 1010 1fff 10rr cycles: 3+L (3/0) MOVE.A s, r 1101 01rr MOVE.A r, s 1101 10rr cycles: 7 (2/0) MOVE.g m, t 1000 0001 1010 gggg 0000 mttt MOVE.g t, m 1000 0001 1010 gggg 0001 mttt cycles: 6+L (6/0) MOVE.W m, t 0001 0000 mttt MOVE.W t, m 0001 0001 mttt cycles: 19 (3/0) MOVE.A m, d 0001 0011 0m0d cycles: 8 (3/0) MOVE.4 m, d 0001 0011 1m0d cycles: 7 (3/0) MOVE.A PC, m 1000 0001 1011 010m cycles: 9 (4/0) MOVE.X ST, C 0000 1001 MOVE.X C, ST 0000 1010 cycles: 5 (2/0) MOVE.A ID, C 1000 0000 0110 cycles: 11 note: ID is read from chip with DAISY-IN line high and configuration flag low. register to/from memory: MOVE.f m, @d 0001 0101 0m0d 0fff cycles: 16+L (3/l) MOVE.n m, @d 0001 0101 1m0d xxxx cycles: 15+L (3/l) MOVE.A m, @d 0001 0100 0m0d cycles: 17 (3/5) MOVE.B m, @d 0001 0100 1m0d cycles: 14 (3/2) MOVE.f @d, m 0001 0101 0m1d 0fff cycles: 17+L (3+L/0) MOVE.n @d, m 0001 0101 1m1d xxxx cycles: 16+L (3+L/0) MOVE.A @d, m 0001 0100 0m1d cycles: 18 (8/0) MOVE.B @d, m 0001 0100 1m1d cycles: 15 (5/0) immediate to register: MOVE.1 h, P 0010 hhhh cycles: 2 (2/0) MOVE.Pn h, C 0011 xxxx hhhh ... hhhh cycles: 2+L (2+L/0) MOVE.Pn h, A 1000 0000 1000 0010 xxxx hhhh ... hhhh cycles: 5+L (5+L/0) MOVE.2 h, d 0001 1d01 hhhh hhhh cycles: 4 (4/0) MOVE.4 h, d 0001 1d10 hhhh hhhh hhhh hhhh cycles: 6 (6/0) MOVE.5 h, d 0001 1d11 hhhh hhhh hhhh hhhh hhhh cycles: 7 (7/0) Flags affected: None. NEG dst In HEX mode, peform twos-complement negation on a register field. In DEC mode, compute nines complement of register field and add one. NEG.f r 1011 1fff 10rr cycles: 3+L (3/0) NEG.A r 1111 10rr cycles: 7 (2/0) Flags affected: Carry is set if register field was 0 before negation, cleared otherwise. NOT dst In HEX mode, perform logical NOT on the bits of a register field. In DEC mode, compute nines complement of a register field. NOT.f r 1011 1fff 11rr cycles: 3+L (3/0) NOT.A r 1111 11rr cycles: 7 (2/0) Flags affected: Carry always cleared. OR src, dst Peform logical OR between register fields. OR.g s, r 0000 1110 gggg 10rr OR.g r, s 0000 1110 gggg 11rr cycles: 4+L (4/0) Flags affected: None. OUT src Transfer nibbles from the C register to the OUT register. OUT.S C 1000 0000 0000 cycles: 4 (3/0) note: transfers nibble 0 of C, not the S field (nibble 15). OUT.X C 1000 0000 0001 cycles: 6 (3/0) Flags affected: None. POP dst Pop A-field of C from return stack. POP.A C 0000 0111 cycles: 8 (2/0) Flags affected: None. PUSH reg Push A-field of C on return stack. PUSH.A C 0000 0110 cycles: 8 (2/0) Flags affected: None. RESET Issue the RESET bus command; chained chips perform a local reset. Unconfigures all soft-configured devices. RESET 1000 0000 1010 cycles: 6 (3/0) Flags affected: None. RET Return from subroutine call (pop top of return stack into PC). RET 0000 0001 cycles: 9 (2/0) Flags affected: None. RETBC n, reg Return from subroutine if bit n of reg is clear (0). RETBC h, A 1000 0000 1000 0110 hhhh 0000 0000 RETBC h, C 1000 0000 1000 1010 hhhh 0000 0000 cycles: 16 (return taken) (7/0) 9 (not taken) RETBC h, ST 1000 0110 hhhh 0000 0000 cycles: 14 (return taken) (5/0) 7 (not taken) Return from subroutine if bits in HST corresponding to bits in h are all 0. RETBC h, HST 1000 0011 hhhh 0000 0000 cycles: 13 (return taken) (5/0) 6 (not taken) Flags affected: Carry is set if return is taken, cleared if not taken. RETBS n, reg, target Return from subroutine if bit n of reg is set (1). RETBS h, A 1000 0000 1000 0111 hhhh 0000 0000 RETBS h, C 1000 0000 1000 1011 hhhh 0000 0000 cycles: 16 (return taken) (7/0) 9 (not taken) RETBS h, ST 1000 0111 hhhh 0000 0000 cycles: 14 (return taken) (5/0) 7 (not taken) Flags affected: Carry is set if return is taken, cleared if not taken. RETCC Return from subroutine if carry flag is clear. RETCC 0101 0000 0000 cycles: 10 (return taken) (3/0) 3 (not taken) Flags affected: None. RETCS Return from subroutine if carry flag is set. RETCS 0100 0000 0000 cycles: 10 (return taken) (3/0) 3 (not taken) Flags affected: None. RETCLRC Return from subroutine call and clear carry. RETCLRC 0000 0011 cycles: 9 (2/0) Flags affected: Carry is cleared. RETEQ src1, src2 Return from subroutine if register fields are EQual. RETEQ.f r, s 1001 0fff 00rr 0000 0000 RETEQ.A r, s 1000 1010 00rr 0000 0000 cycles: 13+L (return taken) (5/0) 6+L (not taken) Return from subroutine if P is EQual to h. RETEQ.1 P, h 1000 1001 hhhh 0000 0000 cycles: 13 (return taken) (5/0) 6 (not taken) Flags affected: Carry is set if return is taken, cleared if not taken. RETGE src1, src2 Return from subroutine if src1 is Greater than or Equal to src2. RETGE.f r, s 1001 1fff 10rr 0000 0000 RETGE.A r, s 1000 1011 10rr 0000 0000 cycles: 13+L (return taken) (5/0) 6+L (not taken) Flags affected: Carry is set if return is taken, cleared if not taken. RETGT src1, src2 Return from subroutine if src1 is Greater Than src2. RETGT.f r, s 1001 1fff 00rr 0000 0000 RETGT.A r, s 1000 1011 00rr 0000 0000 cycles: 13+L (return taken) (5/0) 6+L (not taken) Flags affected: Carry is set if return is taken, cleared if not taken. RETI Return from interrupt. Re-enables interrupt system. RETI 0000 1111 cycles: 9 (2/0) Flags affected: None. RETLE src1, src2 Return from subroutine if src1 is Less than or Equal to field in src2. RETLE.f r, s 1001 1fff 11rr 0000 0000 RETLE.A r, s 1000 1011 11rr 0000 0000 cycles: 13+L (return taken) (5/0) 6+L (not taken) Flags affected: Carry is set if return is taken, cleared if not taken. RETLT src1, src2 Return from subroutine if src1 is Less Than src2. RETLT.f r, s 1001 1fff 01rr 0000 0000 RETLT.A r, s 1000 1011 01rr 0000 0000 cycles: 13+L (return taken) (5/0) 6+L (not taken) Flags affected: Carry is set if return is taken, cleared if not taken. RETNE src1, src2 Return from subroutine if src1 is Not Equal to src2. RETNE.f r, s 1001 0fff 01rr 0000 0000 RETNE.A r, s 1000 1010 01rr 0000 0000 cycles: 13+L (return taken) (5/0) 6+L (not taken) Return from subroutine if P is Not Equal to h. RETNE.1 P, h 1000 1000 hhhh 0000 0000 cycles: 13 (return taken) (5/0) 6 (not taken) Flags affected: Carry is set if return is taken, cleared if not taken. RETNZ reg Return from subroutine if field in reg is Not Zero. RETNZ.A r 1000 1010 11rr 0000 0000 RETNZ.f r 1001 0fff 11rr 0000 0000 cycles: 13+L (return taken) (5/0) 6+L (not taken) Flags affected: Carry is set if return is taken, cleared if not taken. RETSETC Return from subroutine call and set carry. RETSETC 0000 0010 cycles: 9 (2/0) Flags affected: Carry is set. RETSETXM Return from subroutine call and set XM bit in status register. RETSETXM 0000 0000 cycles: 9 (2/0) Flags affected: XM bit in HST is set. RETZ reg Return from subroutine if field in reg is Zero. RETZ.f r 1001 0fff 10rr 0000 0000 RETZ.A r 1000 1010 10rr 0000 0000 cycles: 13+L (return taken) (5/0) 6+L (not taken) Flags affected: Carry is set if return is taken, cleared if not taken. RLN dst Rotate nibbles left in the specified field of dst. RLN.W r 1000 0001 00rr cycles: 21 (4/0) Flags affected: None. RRN dst Rotate nibbles right in the specified field of dst. RRN.W r 1000 0001 01rr cycles: 21 (4/0) Flags affected: SB is set if the nibble rotated from nibble 0 to nibble 15 was non-zero. RSI ReSet Interrupts. Causes any input register line high to be considered a new interrupt regardless of whether all input register lines have returned low. Documents disagree on opcode; some say 8081, most say 80810. RSI 1000 0000 1000 0001 0000 cycles: 6 Flags affected: None. SETB n, dst Set bit n of dst (make it 1). SETB h, A 1000 0000 1000 0101 hhhh SETB h, C 1000 0000 1000 1001 hhhh cycles: 6 (5/0) SETB h, ST 1000 0101 hhhh cycles: 4 (3/0) Flags affected: None. SETDEC Set DEC (BCD) arithmetic mode. SETDEC 0000 0101 cycles: 3 (2/0) Flags affected: None. SETHEX Set HEX (binary) arithmetic mode. SETHEX 0000 0100 cycles: 3 (2/0) Flags affected: None. SHUTDN Issue the NOP bus command to clear all ops, then issue the SHUTDOWN bus command and enter low-power standby state; chained chips respond according to their own special requirements. System clock and on-board oscillator are stopped. Data in CPU resident memory is preserved. However, if SHUTDN is executed when the output register is 000, the PC will be set to zero, causing a system halt. The CPU is reawakened by either pulling an input register line high, or by driving the NCD line low then releasing it when NSTR (system clock) goes low (active). SHUTDN 1000 0000 0111 cycles: 6 (3/0) Flags affected: None. SLN dst Shift register field left by one nibble. A zero nibble is shifted in on the right. SLN.f r 1011 1fff 00rr cycles: 3+L (3/0) SLN.A r 1111 00rr cycles: 7 Flags affected: None. SRB dst Shift register field right by one bit. A zero bit is shifted in on the left. SRB.g r 1000 0001 1001 gggg 00rr cycles: 6+L SRB.W r 1000 0001 11rr cycles: 20 (4/0) Flags affected: SB is set if a one is shifted out on the right. SREQ Issue the POLL bus command and latch system bus into C.0; HS2 (aka SR, the Service Request hardware status bit) is set if C.0 is not zero (each bit representing one device's response). SREQ 1000 0000 1110 cycles: 7 (3/0) Flags affected: SR bit in HST is set if C.0 is non-zero. SRN dst Shift register field right by one nibble. A zero nibble is shifed in on the left. SRN.f r 1011 1fff 01rr cycles: 3+L (3/0) SRN.A r 1111 01rr cycles: 7 Flags affected: SB is set if the nibble shifted off the right was non-zero. SUB src, dst Perform subtraction. register field to register field: SUB.f s, r 1011 0fff 00rr SUB.f r, s 1011 0fff 10rr cycles: 3+L (3/0) SUB.A s, r 1110 00rr SUB.A r, s 1100 10rr cycles: 7 (2/0) immediate to register field: SUB.g n, r 1000 0001 1000 gggg 10rr xxxx cycles: 5+L note: always performed in HEX mode SUB.A n, d 0001 1d00 xxxx cycles: 7 (3/0) note: always performed in HEX mode SUBN src, dst Perform subtract negative (dst = src - dst). SUBN.f s, r 1011 0fff 11rr cycles: 3+L (3/0) SUBN.A s, r 1110 11rr cycles: 7 (2/0) SWAP src, dst Exchange contents of register fields. SWAP.f s, r 1010 1fff 11rr cycles: 3+L (3/0) SWAP.A s, r 1101 11rr cycles: 7 (2/0) SWAP.g m, t 1000 0001 1010 gggg 0010 mttt cycles: 6+L SWAP.W m, t 0001 0010 mttt cycles: 19 (3/0) SWAP.A m, d 0001 0011 0m1d cycles: 8 (3/0) SWAP.4 m, d 0001 0011 1m1d cycles: 7 (3/0) SWAP.1 P, C.n 1000 0000 1111 nnnn cycles: 6 (4/0) SWAP.X C, ST 0000 1011 cycles: 5 (2/0) SWAP.A m, PC 1000 0001 1011 011m cycles: 16 (4/0) UNCNFG Unconfigure the configured device @C.A; it then will only respond to the CONFIGURE and ID bus commands. UNCNFG 1000 0000 0100 cycles: 12 (3/0) DISASSEMBLY SUMMARY Here instructions are listed in order of opcode. Abbreviations: Also see the SYMBOL KEY. p, q: opcode specifier bits. Definitions follow instructions. = 0 = 0000 0000 RETSETXM 0000 0001 RET 0000 0010 RETSETC 0000 0011 RETCLRC 0000 0100 SETHEX 0000 0101 SETDEC 0000 0110 PUSH.A C 0000 0111 POP.A C 0000 1000 CLR.X ST 0000 1001 MOVE.X C, ST 0000 1010 MOVE.X ST, C 0000 1011 SWAP.X C, ST 0000 1100 INC.1 P 0000 1101 DEC.1 P 0000 1110 gggg 00rr AND.g s, r 0000 1110 gggg 01rr AND.g r, s 0000 1110 gggg 10rr OR.g s, r 0000 1110 gggg 11rr OR.g r, s 0000 1111 RETI = 1 = 0001 0000 mttt MOVE.W m, t 0001 0001 mttt MOVE.W t, m 0001 0010 mttt SWAP.W m, t 0001 0011 pmqd MOVE/SWAP .A/.4 m, d q p m d 0 MOVE 0 .A 0 A 0 D0 1 SWAP 1 .4 1 C 1 D1 0001 0100 pmqd MOVE p q 0 .A m, @d 1 .B @d, m 0001 0101 0m0d gggg MOVE.g m, @d 0001 0101 0m1d gggg MOVE.g @d, m 0001 0101 1m0d xxxx MOVE.n m, @d 0001 0101 1m1d xxxx MOVE.n @d, m 0001 011d xxxx ADD.A n, d 0001 1000 xxxx SUB.A n, D0 0001 1001 hhhh hhhh MOVE.2 h, D0 0001 1010 hhhh hhhh hhhh hhhh MOVE.4 h, D0 0001 1011 hhhh hhhh hhhh hhhh hhhh MOVE.5 h, D0 0001 1100 xxxx SUB.A n, D1 0001 1101 hhhh hhhh MOVE.2 h, D1 0001 1110 hhhh hhhh hhhh hhhh MOVE.4 h, D1 0001 1111 hhhh hhhh hhhh hhhh hhhh MOVE.5 h, D1 = 2 = 0010 hhhh MOVE.1 h, P = 3 = 0011 xxxx hhhh ... hhhh MOVE.Pn h, C = 4 = 0100 0000 0000 RETCS 0100.bbbb bbbb BRCS PC+b+1 = 5 = 0101 0000 0000 RETCC 0101.bbbb bbbb BRCC PC+b+1 = 6 = 0110.bbbb bbbb bbbb JUMP.3 PC+b+1 = 7 = 0111.bbbb bbbb bbbb CALL.3 PC+b+1 = 80 = 1000 0000 0000 OUT.S C 1000 0000 0001 OUT.X C 1000 0000 0010 IN.4 A 1000 0000 0011 IN.4 C 1000 0000 0100 UNCNFG 1000 0000 0101 CONFIG 1000 0000 0110 MOVE.A ID, C 1000 0000 0111 SHUTDN 1000 0000 1000 0000 INTON 1000 0000 1000 0001 0000 RSI 1000 0000 1000 0010 xxxx hhhh ... hhhh MOVE.Pn h, A 1000 0000 1000 0011 BUSCB 1000 0000 1000 mm00 hhhh CLRB h, m 1000 0000 1000 mm01 hhhh SETB h, m 1000 0000 1000 mm10 hhhh 0000 0000 RETBC h, m 1000 0000 1000 mm10 hhhh.bbbb bbbb BRBC h, m, PC+b+5 1000 0000 1000 mm11 hhhh 0000 0000 RETBS h, m 1000 0000 1000 mm11 hhhh.bbbb bbbb BRBS h, m, PC+b+5 mm 01 A 10 C 1000 0000 1000 1100 JUMP.A @A 1000 0000 1000 1101 BUSCD 1000 0000 1000 1110 JUMP.A @C 1000 0000 1000 1111 INTOFF 1000 0000 1001 ADD.A P+1, C 1000 0000 1010 RESET 1000 0000 1011 BUSCC 1000 0000 1100 hhhh MOVE.1 P, C.h 1000 0000 1101 hhhh MOVE.1 C.h, P 1000 0000 1110 SREQ 1000 0000 1111 hhhh SWAP.1 P, C.n = 81 = 1000 0001 00rr RLN.W r 1000 0001 01rr RRN.W r 1000 0001 1000 0fff 00rr xxxx ADD.f n, r 1000 0001 1000 1fff 00rr xxxx SUB.f n, r 1000 0001 1001 gggg 00rr SRB.g r 1000 0001 1010 gggg 0000 mttt MOVE.g m, t 1000 0001 1010 gggg 0001 mttt MOVE.g t, m 1000 0001 1010 gggg 0010 mttt SWAP.g m, t 1000 0001 1011 001m JUMP.A m 1000 0001 1011 010m MOVE.A PC, m 1000 0001 1011 011m SWAP.A m, PC 1000 0001 11rr SRB.W r = 82 - 8F = 1000 0010 hhhh CLRB n, HST 1000 0011 hhhh 0000 0000 RETBC n, HST 1000 0011 hhhh.bbbb bbbb BRBC n, HST, PC+b+3 1000 0100 hhhh CLRB n, ST 1000 0101 hhhh SETB n, ST 1000 0110 hhhh 0000 0000 RETBC n, ST 1000 0110 hhhh.bbbb bbbb BRBC n, ST, PC+b+3 1000 0111 hhhh 0000 0000 RETBS n, ST 1000 0111 hhhh.bbbb bbbb BRBS n, ST 1000 1000 hhhh 0000 0000 RETNE P, n 1000 1000 hhhh.bbbb bbbb BRNE P, n 1000 1001 hhhh 0000 0000 RETEQ P, n 1000 1001 hhhh.bbbb bbbb BREQ P, n 1000 101p qqrr 0000 0000 RETcc.A r, s 1000 101p qqrr.bbbb bbbb BRcc.A r, s, PC+b+3 pqq cc 000 EQ r, s 001 NE r, s 010 Z r 011 NZ r 100 GT r, s 101 LT r, s 110 GE r, s 111 LE r, s 1000 1100.bbbb bbbb bbbb bbbb JUMP.4 PC+b+2 1000 1101 bbbb bbbb bbbb bbbb bbbb JUMP.A b 1000 1110.bbbb bbbb bbbb bbbb CALL.4 PC+b+2 1000 1111 bbbb bbbb bbbb bbbb bbbb CALL.A b = 9 = 1001 pfff qqrr.0000 0000 RETcc.f r, s 1001 pfff qqrr.bbbb bbbb BRcc.f r, s, PC+b+3 pqq cc 000 EQ r, s 001 NE r, s 010 Z r 011 NZ r 100 GT r, s 101 LT r, s 110 GE r, s 111 LE r, s = A - F = 101p pfff qqrr arithmetic .f 11pp qqrr arithmetic .A ppqq 0000 ADD s, r 0001 ADD r, r 0010 ADD r, s 0011 DEC r 0100 CLR r 0101 MOVE s, r 0110 MOVE r, s 0111 SWAP r, s 1000 SUB s, r 1001 INC r 1010 SUB r, s 1011 SUBN s, r 1100 SLN r 1101 SRN r 1110 NEG r 1111 NOT r